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Materials and processes for high-k gate stacks
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C.M. Osburn, A. Kingon, G. Lucovsky, J.P. Maria, V. Misra & G. Parsons, North Carolina State University, USA, S.A. Campbell, University of Minnesota,USA, E. Eisenbraun, University of Albany, USA, E. Garfunkel & T. Gustafson, Rutgers University, USA, D. L. Kwong & J. Lee, University of Texas at Austin, USA, T.P. Ma,Yale University, USA, D. Schlom, Penn State University, USA, & S. Stemmer,UC Santa Barbara, USA
ABSTRACT
Considerable progress has been made in identifying materials and processes for high k gate stacks which meet the ITRS leakage requirements. Nitrided Hafniumsilicates have been shown to possess the requisite thermal stability for equivalent oxide thicknesses (EOT) below about 1 nm. Gate electrodes of TaSiN, Ru, or Ru/Ta alloys also appear to meet the stability requirements and possess appropriate work functions. The current challenge is in meeting the device electrical requirements: low charge levels, high channel mobility, and long-term stability during stressing. Longer term, the challenge is in reducing the thickness of the interfacial layer to facilitate EOTs down to 0.5 nm.
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