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Intel Developer Forum hits town, monumental hype-fest ensues |
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Sep 19, 2007 at 10:28 AM |
When the Intel Developer Forum hits town, prepare for a self-congratulatory hype-fest of monumental proportions.
The fall 2007 edition blasted off yesterday in San Francisco, where Paul "We're Number One!" Otellini, Intel's president/CEO, opined that this IDF would be the best ever. If the first day's parade of code-names, production ramp news, and technical breakthrough announcements is any indication, the IDF Fall 2007 will certainly challenge for the honor of being one of the noisiest forums ever, with a few clear signals penetrating the corporate boosterism.
First, the code names. You've got your McCreary (not O'Riley) dual-/quad-core security management, your Eaglelake (not Duckpond) chipset, your Danbury (not Langley) data encryption, your Tolapi (not Tilapia) system on a chip, and your Silverthorne (not Blackwater) processor family. And, of course, there's the Penryn (not Penguin) processor, which debuted last November.
Code-name Nehalem (for business computer architectures) is another newbie. This handle elicits a smirk because of the similarity between the "real" spelling and its backward version---Melahen---both of which sound like the names of villages in some Middle Eastern land. Somewhere deep within an Intel cubicle farm or nanoscale chip fab, I can imagine people chanting "Nehalem Melahen, Nehalem Melahen," letting their geek chi flow in a brand-imprinting meditative trance.
Speaking of the Penguin, er Penryn, and NehaleMelahen 45-nm designs, both incorporate the hafnium-based high-k metal gate (HKMG) secret-sauce developed by Intel. The first volume batches of Penryn family devices, energy efficient with 20% better performance stats, will come out of the fabs on November 12, which seems an odd choice for a launch date, since that Monday is also Veterans Day, a U.S. national holiday honoring those who've served in the armed forces.
After demoing the NehaleMelahen designs for the first time, Otellini told the gathered flock that the new chips will hit the market in the second half of 2008. But before that, by 1Q08, some 34 45-nm designs will be released. Turning a charming shade of green, the Intel honcho also noted that by next year, all of the company's 65- and 45-nm devices will be encased in halogen-free packaging.
While discussing the next-next process-node generation, Otellini proudly showed off what was touted as the world's first 300-mm wafer with 32-nm SRAM test chips. In sync with Intel's self-described "tick-tock strategy" of alternating new design architectures and silicon technology ramps every other year (and also a timely reminder to AMD and others that the clock is always ticking when you compete with Intel), he said the 32-nm families---they of the nearly 2 billion transistors per die---will be production-ready starting in 2009.
Whether in open session or over a cold one or three, I expect (one can hope) more process details to emerge about Intel's newer 45-nm designs as well as the 32-nm newborn (and its HKMG Version 2.0) at this year's IEEE International Electron Devices Meeting (IEDM) to be held Dec. 10-12 in Washington, DC.
If you want more of Intel's prodigious spin on its fall '07 IDF, including corpo-blogs, podcasts, and assorted YouTube-ishness, click here.
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