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Livin' large in Leuven: IMEC's Ronse touts litho projects, disses nanoimprint |
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Oct 16, 2007 at 09:38 AM |
It's IMEC's research review meeting week in Leuven and Brussels, which kicked off with a pack of journos from around the globe descending on the research center for two days of presentations and meetings.
Given the Belgian outfit's intensive efforts in lithography (they claim world leadership status), one of the more keenly awaited presentations (at least for those of us with a development and manufacturing bent) came from Kurt Ronse, IMEC's guru of advanced litho.
Kurt went over IMEC's lithographic Big Three options for the 32-nm half-pitch node---high-refractive-index (fluids and lens glass) 193-nm immersion (IML) with single exposure; IML with double patterning; and extreme ultraviolet litho, better known as EUVL. Cutting to the chase, option 1 (high-index IML with single exposure) will be late for the 32-nm party and may be only a single tech-generation solution (the kind of solution that does not make IC makers or their tool suppliers happy). Option 2, IML with double patterning, may be the only one who gets to the party on time, although issues like cost of ownership, tight overlay budgets, and design splits challenges (especially for logic) will not make it easy. Then there's Option 3, EUVL, which doesn't have a hope in Hades of even leaving the house on time, let alone getting to the 32-nm party.
Many of us watching the litho space have become increasingly skeptical about EUVL ever being used for production. Kurt did his best to put a good face on the not-insignificant progress that IMEC, ASML, materials companies, and others have made to push the disruptive technology down the roadmap. He showed recently taken SEM shots of actual vertical and horizontal lines and spaces imaged with the alpha development tool in the 300-mm fab in Leuven. The center also announced it will buy a preproduction EUVL tool from ASML, which will be delivered and installed in 2010. Having a system that actually facilitates full-scale development, with enhanced optics and more powerful source power, will certainly enhance the overall EUVL push.
But will it be enough to get EUVL to the 22-nm half-pitch dance on time?
Despite commendable progress in defect reduction, mask blanks, and resists, the technology's list of daunting challenges has not grown any shorter: not once did I hear the words, "well, we solved that issue, so check it off the list." In certain cases, such as resist line-edge roughness and shadowing, lots of heavy lifting remains. One thing not mentioned by Kurt---the extremely uneconomical pricetag (EUP) of around $100 million (or is it Euro?!)---sits in the EUVL discussion room like the proverbial pachyderm.
So what are the alternatives? How about, hmmm, nanoimprint lithography (NIL)?
When I asked Kurt about NIL, he cited the usual reasons lithographers from the optical camp usually give when dis(s)counting the emerging technology. He sees fundamental issues of overlay capability and defectivity that will never allow NIL, despite some progress made in both areas, to be "a serious candidate for semiconductor applications." He did allow for the possibility of imprint having niche applications in other areas (note to reader---NIL is already used in LED and photonic crystal manufacturing, and has the inside track for next-gen HDD production in a few years). But not for CMOS, he said, and no, there isn't any NIL gear (let alone projects) at IMEC.
In counterpoint to Kurt's dis(s)missal of NIL, Molecular Imprints announced today that Toshiba, one of its key customers, presented info and data from ongoing work with MII's system in one of its fabs. Here's some extracts from the press release:
Molecular Imprints today announced that Toshiba Semiconductor...has validated the use of MII's imprint lithography technology in developing 22-nm node CMOS devices. Toshiba fabricated narrow trenches at dimensions down to 18 nm using MII's Imprio(R) 250 system. Toshiba presented its findings in a paper titled "Nanoimprint Applications Toward 22-nm Node CMOS Devices" at the 33rd International Conference on Micro- and Nano-Engineering (MNE) in Copenhagen, Denmark.
Results detailed in the paper demonstrate the process capability and stability of MII's Step and Flash Imprint Lithography (S-FIL) technology for next-generation semiconductor manufacturing. Significant enhancements over earlier performance in the areas of imaging, defectivity, and overlay control were confirmed. Specifically, Toshiba leveraged MII's Imprio 250 system to pattern 18-nm isolated features and 24-nm dense features with <1-nm critical dimension uniformity (CDU) and <2-nm line edge roughness (LER). Defectivity levels of as low as 0.3 defects per cm squared were achieved, which are approaching those of immersion lithography. Device overlay results were also within Toshiba's required specifications.
My crystal ball is as murky as the next person's, so I can in no way predict the ultimate success or failure of EUVL or NIL. But I definitely would not rule out imprint's chance to make an impact on advanced-node CMOS some day---nor would I expect the EUVL projects' funding to dry up in the near term.
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