Samsung Electronics has revealed that its NAND flash devices at the 30nm node, which it expects to enter volume production in 2009, will adopt a double patterning self-aligned hardmask process that does away with the need for charge trap flash (CTF) technology. 

The self-aligned double patterning technology (SaDPT) looks similar to new process/product introductions made by both Applied Materials and Lam Research earlier this year.

In SaDPT, the 1st pattern transfer is a wider-spaced circuit design of the target process technology, while the 2nd pattern transfer fills in the spaced area with a more closely designed pattern, Samsung said.

Avoiding process issues expected at the 30nm node such as Line-Edge Roughness (LER),
Samsung can utilize existing immersion lithography tools while employing plasma-etch processes to form stacks smaller than the resolution of the optics of the lithography tool.

Samsung expects to fabricate a 64 Gigabit (Gb) multi-level cell (MLC) NAND flash memory chip that can be stacked to a maximum of 16 die to provide a memory card up to 128 Gigabyte (GB).

New product introductions regarding SaDPT-type processes from Applied Materials and Lam Research can be viewed here:

http://www.fabtech.org/content/view/3175/132/

http://www.fabtech.org/content/view/3046/132/