P. H. Haumesser, M. Cordeau, S. Maitrejean & T. Mourier, CEA-LETI and L. G. Gosset & W. F. A. Besling, Philips Semiconductor Crolles R&D and G. Passemard & J. Torres, STMicroelectronics

ABSTRACT

As ultra-large scale integration progresses, efficient copper metallization of the narrow geometries becomes challenging. In this article, the various critical steps of the damascene metallization scheme are identified. Barrier deposition, copper seeding, electroplating and copper lines capping are discussed. For each step, current approaches and related limitations are presented. The main purpose of this contribution is to show that electrochemical wet processes can be efficiently used to address the challenges raised by feature size diminution.