Online information source for semiconductor professionals

P.H. Haumessera, M. Cordeaua, S. Maîtrejeana & T. Mouriera, CEA-LETI, Grenoble, France, L.G. Gosset & W.F.A. Besling, Philips Semiconductors Crolles R&D, Crolles, France, G. Passemardc & J. Torresc, STMicroelectronics, Crolles, France

ABSTRACT

As ultra-large scale integration progresses, efficient copper metallization of the narrow geometries becomes challenging. In this article, the various critical steps of the damascene metallization scheme are identified. Barrier deposition, copper seeding, electroplating and copper lines capping are discussed. For each step, current approaches and related limitations are presented. The main purpose of this contribution is to show that electrochemical wet processes can be efficiently used to address the challenges raised by feature size diminution. Copper electroplating is since long used to fill trenches and vias with metal. New developments in copper electrodeposition such as medium acid chemistries or planarizing copper plating (ECMD) are described. Heterogeneous electrochemical reactions are also used in new barrier deposition techniques alternative to physical vapor deposition (PVD): the atomic layer deposition (ALD) method is one of the most promising. Electroless deposition of self-aligned capping layers above copper lines is discussed as well. At last, it will be shown that wet electrochemical processes can also apply to copper seeding with seed repair techniques or by the mean of very promising electro-grafting processes, which can be used to perform efficient and robust direct to barrier plating.