Written by Andreas Knorr, International SEMATECH/Infineon Technologies and Klaus Pfeifer, International SEMATECH and Bernd Kastenmeier, International SEMATECH/IBM Corp.

ABSTRACT

Relentless device scaling and performance improvements have led to the introduction of low resistance wiring schemes utilizing copper (Cu) interconnects at the 130-nm node technology generation. Equally desirable, but much slower in the development and adaptation proved to be the introduction of low-capacitance interconnect isolation. Degraded thermo-mechanical properties, processing difficulties and increased defectivity were only some of the bumps in the road.