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JD project to tackle DFM adoption issues |
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Feb 04, 2005 at 02:00 AM |
Synopsys and KLA-Tencor are collaborating on a compact yield analysis
and modeling system for Toshiba Corporation. The new modeling system
will enable Toshiba to improve parametric yields on its most advanced
sub-100-nm system-on-chip (SoC) products by predicting the impact of
process variations on final device performance as they occur during
large scale integration (LSI) production.
According to Toshiba, an important goal of this joint project is to
enable improved information sharing between its IC design and process
engineers in order to accelerate the company's advanced process
development and yield ramp efforts. Toshiba will install the new
modeling system at its 300-mm production facility in Oita, Japan, for
use in both low- and high-volume SoC manufacturing.
"Mastering parametric yield is essential for enabling successful IC
production," stated Shigeru Komatsu, chief knowledge and infrastructure
officer of Toshiba Semiconductor."Since SoC product lifecycles are
typically shorter than other devices, less process data can be
collected to optimize the manufacturing process, making it all the more
imperative that we get our processes right the first time. Having the
ability to model device performance based on real-time parametric yield
data will allow us to make rapid decisions during production to
fine-tune our processes and optimize our yields, as well as ensure we
continue to meet our time-to-market requirements."
"TCAD models have been utilized in leading-edge semiconductor R&D
applications for decades," stated Lars Bomholt, group director at
Synopsys."By applying these proven models in manufacturing yield
analysis with the help of KLA-Tencor's Klarity ACE XP product, we can
provide our customers with a model-based method to relate the many
variables in semiconductor device manufacturing to the electrical
properties of the final product."
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