A flurry of announcements from companies large and small in the design for manufacturing/design for manufacturability ("DFM," whichever way you define it) space underscore the continuing efforts to narrow the gap between those who design and those who develop the processes that make chips.
With the upcoming Semicon West (week of July 10) and Design Automation Conference (week of July 24) events taking place at the Moscone Center in San Francisco, the flurry is likely to turn into a blizzard of news and hype in the coming weeks.
Segment leaders Cadence and Synopsys, up-and-comer Sagantec, and newbie Pyxis contributed to this current spike in DFM PR machinations. In terms of the signal-to-noise ratio (or the tough-to-puff ratio, as some of us in the news biz like to say), each player manages to provide a bit of signal/toughness.
Let's start with the little guy, Pyxis. The company now has more money in the till, after a cool $9.2 million came in from a Series B funding round (led by Formative Ventures of Menlo Park). The start-up's goal? "To capitalize on the need for a true DFM routing solution," says its president and CEO, Naeem Zafar. Pyxis is one of a slew of start-up and early-stage companies vying for share of the emerging DFM market, a market that continues to curry favor in--and thus wrest some cash from--many in the venture capital and angel investor ranks.
Synopsys's and Sagantec's announcements have some application overlap in the tricky area of lithography-related "hot spots." Sagantec says its DFM-Fix is "the first announced product that solves the ... 'hot spot' problem at the design data stage." Synopsys, in touting the latest rev of its IC Compiler place-and-route tool, notes the inclusion of a new capability for "lithography hot-spot fixing, but with limited customer availability" (among several other enhancements). Since litho-caused process variations often bedevil 65- and 45-nm designs, any additions to the DFM toolbox will be greatly appreciated--as long as they work, of course.
The strongest signal of the day, though, emanates from Cadence, which introduced its Precision Router chip-and-block routing tool. The company claims the new system "speeds design and manufacturing convergence by allowing designers to model manufacturing effects during the design process." (Ah, modeling rears its simulated head once again.)
Any PR announcement that includes decent testimonial quotes from a major customer almost always grabs a higher credibility index rating, and in Cadence's case, the EDA power got none other than a couple of IBM honchos to "say" a few words. Sure, quotes in press releases have been massaged well beyond the point of spontaneity (especially when corporate legal departments are involved), but nonetheless, one of the IBM statements caught my attention.
Mention of "a single platform for design-for-manufacturing and design-for-yield interconnect optimization and creation" by Big Blue's Mark Papermaster (great last name, that) suggests that maybe, just maybe, Cadence has succeeded in getting closer to the holy grail of DFM--a unified, single, soup-to-nuts platform for bridging the gap between the drawing board and the production floor, a shining path to the sweet spot where physical, electrical, and logical considerations converge at the designer's fingertips, and dealing with process variabilities, first-order manufacturing effects, and design-rule complexities becomes routine.
Sounds grand, doesn't it? Or perhaps it sounds too good to be true. As the cliches go, the market will decide, and the technology doesn't lie.
But the daunting challenges posed by making sense of several zillion data points and actually being able to do something with those data, as well as getting design guys and manufacturing folks to communicate and maybe even understand each other continue to provide grist for the skeptics.
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