Home
News
Blogs
Fabtech Jobs
Product Briefings
Going Places
300mm Activity Reports
Core Sections
Wafer Processing
Lithography
Fab management
Materials & Gases
Critical Components
Cleanroom
EHS
 
Find

GlobalSpec - The Engineering Search Engine
 
Home arrow Blogs arrow Chip Shots arrow Blogs arrow Sampling IEDM's collective brainpower one paper at a time
Sampling IEDM's collective brainpower one paper at a time Print E-mail
Dec 12, 2006 at 04:22 PM
Trying to cover the IEDM conference is a daunting task. The sheer magnitude of the event---with seven parallel sessions this morning and 38 sessions overall---makes it nearly impossible to get more than a sampling of the collective brainpower of the extended electron devices community.

After coming in off the rainy San Francisco streets, I made it to the session on CMOS devices focused on advanced gate stacks to hear the invited paper from IMEC and several of its chipmaker partners. The presentation discussed the latest work from the Belgian research center evaluating the manufacturability of nickel-based fully silicided (FUSI) metal gates for the 45-nm node and beyond. FUSI team member Jorge Kittl presented data on process integration, process control, reliability, device design, and circuit-level benefits. The conclusions reached strenghten the argument for FUSI as a replacement for conventional polysilicon gate stacks.

Among the findings, tests show that FUSI meets the requirements for diffierent material options. Phase control--related process variabilities can be optimized successfully, and FUSI enables a lowering of the thermal budget without increasing the depletion of poly. There seems to be no mobility degradation intrinsic to FUSI, and it is compatible with strain techniques, according to Kittl. An optimized FUSI/HfSiON transistor has shown high performance attributes with low leakage characteristics.

After this glimpse into the front-end-of-line world of advanced transistor formation, I jumped over to the emerging technologies session for something completely different. Duke University biochemist Thom LaBean shared an overview of ongoing work on self-assembling DNA nanostructures and DNA-based nanofabrication. This kind of research takes its inspiration from the host of "self-assembling molecular machines" found in the realm of biology, said LaBean. The goal is the fabrication of nanoelectronic components through biomolecular fabrication techniques.

While such techniques are a long, long way from translating into manufacturable techniques and replacing CMOS processes, their potential is vast. LaBean showed experimental results of TAO tile lattices and nanotubes, 4 X 4 crosstile lattices and nanotubes, and metal nanowires templated on DNA. Such lattices can be used to position materials down to the nanoscale.

"We can assemble micron-scale materials with nanometer feature precision," he said, showing a "nice, repetitive lattice" with 19-1/2 nm pitch. He also shared AFM images of highly conductive nanowires created with electroless deposition on complex DNA, with sizes down to 15 nm.

One of the big questions is, how can DNA self-assembly be useful? LeBean says such techniques could "build a complete structure, [be] used as a template, or used to place components on previously built structures." Some assembly might be "relative to lithographic features for electronics and photonic devices." The deposition of DNA could be done on other structures as well. Future directions include pattern formation with various DNA assembly methods and the 3-D alignment of layers, as well as prototyping new DNA "building blocks."

I wonder whether any of these exotic, lab-based techniques might actually be somehow integrated into a CMOS flow, hence extending the time-tested process farther down the roadmap, or whether they must be considered another strictly post-CMOS technology candidate.

Speaking of 3-D structures, the third and final paper I heard this morning came from a team at IBM's Watson Research Center. The topic focused on structure, design, and process control for copper bonded interconnects in 3-D ICs.

According to the results presented, the group has made significant progress in copper-to-copper bonding, including such areas as interconnect geometries and pattern density effects, the quality of the bonding itself, stacked layer alignment accuracy, electrical connection between the bonded layers, contact resistance measurements, and thermal reliability of bonded layers. The Big Blue Wrecking Crew is very encouraged by the demonstration data seen in the mechanical, electrical, and alignment accuracy results, thus lending credence to the eventual efficacy---and even manufacturability---of 3-D integration based on copper bonding techniques.

There are few conferences like IEDM where one can have such a dizzying technical tour of top-level work in both the transistor and interconnect realms, as well as a glimpse of the futuristic potential of self-assembled DNA nanostructures.
Readers' comments



Bookmark with:
DeliciousDiggredditStumbleUpon

Visit Fabtech Jobs websiteSubscribe to Fabtech weekly newsletter

Related articles
Intel dodges bullet with 45-nm high-k metal gate breakthrough, finds a home on YouTube   (13/11/2007)
CEMMNT and Taylor Hobson announce Metrology Open Day  (02/11/2007)
IEDM paper makes case that laser annealing's time may have come   (13/12/2006)
Sampling IEDM's collective brainpower one paper at a time  (12/12/2006)
SPIE Microlithography Conference  (20/02/2006)

Related jobs
Process Engineers  (Balzers , 06/06/2008)
Development Engineers Power-Semiconductor Devices and Power-Modules  (Reutlingen, 19/05/2008)
CAD Support Engineer  (Greenock, Scotland, 16/04/2008)
Global Project Coordinator Solar Laboratory  (Alzenau, 28/11/2007)
Service Technician  (Stuttgart, 24/08/2007)
Most Popular Blogs
MICRO Archive
News Feed
Blog Archive
Blog & Website Roll