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IEDM paper makes case that laser annealing's time may have come |
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Dec 13, 2006 at 12:19 PM |
Laser annealing has been a next-generation process for a few generations, so the question has been: when will it actually move into production? Since junction scaling is one of the most, if not the most, critical factors to scale transistors beyond 45 nm, advanced junction technologies such as plasma doping, cluster ion beam, and laser annealing will need to be added to the process toolbox.
A Session 33 paper from a combined Samsung R&D and Ultratech team made a compelling case for the integration of laser spike annealing (LSA) for reactivation purposes on metal-gate CMOS devices (in this case, a tungsten gate), specifically for sub-50-nm DRAMs.
The groundbreaking Samsung study showed how LSA was used to get a nice pop in the drive currents of both peripheral and cell transistors without suffering from short channel effects, while minimizing the typically pesky pattern effect problem around the metal gate. The data also indicated that both junction and gate-induced drain leakage levels were improved without generating laser-induced local defects or reliability degradation. Across the board, LSA received high marks in the research.
Granted, this work was done in an R&D environment, not a pilot or production line. But the results suggest that laser annealing might become mainstream for certain applications sooner rather than later.
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