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Post-IEDM musings: 3-D metrology challenges = opportunities |
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Dec 18, 2006 at 07:45 AM |
A statement made during the last IEDM paper I heard last week jarred loose one of those "same as it ever was" moments.
During his talk on performance and variability comparisons between multigate FETs (those lovable MUGFETs) and planar silicon-on-insulator transistors, the Freescale researcher (sorry, I missed his name) said "it is very challenging to do in-line gate dimension and profile metrology on the side of the fin."
When I heard that comment slip out, I said to myself, "no kidding!" (Actually, it was stronger language.)
I've heard about the difficulties of measuring the third dimension of chip architectures since copper first started migrating into the back end of line and increasingly high aspect ratios became more prevalent. It's not easy to get a good look at the side of a vertically oriented feature with top-down metrology tools.
With FinFETS and MUGFETs coming soon in the transistor realm and 3-D interconnect and packaging looming in the back end, another raft of challenges faces engineers trying to extricate 45- and 32-nm processes out of development and into production. Without good metrology, forget about scaling these very finicky processes into reasonably yielding manufacturability.
But the semiconductor community has long mastered making technological lemondade out of the proverbial lemons. When a technical gauntlet is thrown down, someone usually rises to the challenge. I look forward to finding out how the 3-D-feature in-line metrology challenge is met.
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