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Oct 22, 2007 at 10:26 AM |
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News from last week’s AMD conference call that told us the company would start production of 45nm microprocessors in the first half of 2008 shouldn’t be looked at from the point of view of ‘volume production.’ The message that should be taken from the news is that at some time in the first six months of next year, AMD may well have a small amount of devices entering the supply-chain.
AMD had said that we should see 45nm chips ‘mid-year,’ which could easily have applied to the time period from June through September based on Barcelona schedules!
A key aspect for AMD’s coming out with this revised 45nm schedule could be that yields have been good, prompting an earlier-than-expected launch date. AMD has one big advantage over Intel at the 45nm node, namely the ability to push out the adoption of high-k dielectrics and metal gates until the 32nm node due to the use of SOI wafers.
Process tweaks will still be required especially in post-immersion litho processing. So too will strain engineering, which is still controlling gate leakage levels without the benefit of high-k.
In many respects we regard the 65nm to 45nm migration by AMD as more of a litho-friendly design shrink than a fundamental process switch compared to that of Intel’s migration.
Over the next several quarters we are anticipating that AMD will ramp Fab 36 to full capacity with the vast majority of production at the 65nm node. The 45nm migration should start ‘mid-year,’ but with new immersion tools required, both qualified and ramped, we would still expect ‘volume production’ to be in 2009, not 2008, with a significant amount of Fab 36 production switched to 45nm by 2Q09.
Two key aspects that could see the 45nm ‘volume ramp’ coming earlier are the facts that 45nm yields are above expectations, and also that immersion litho tool orders are placed early enough in that yield target achievement for the tools to be delivered and qualified to enable the ramp.
Currently, immersion tool delivery times are long and are close to 10 months or more depending on NA spec. AMD may go ‘blind’ and order the tools now so that a ‘volume’ ramp could happen in the second half of the year. We haven’t as yet picked up on that actually happening, but it is possible!
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Comment by GUEST on 2007-10-31 09:20:46
The high-k is not used for performance enhancement per se, it is used for gate leakage reduction so that the oxide thickness can be reduced further for higher performance. But reduction is not the only route. Straining the silicon gives you the most for a given scaling. High-k is certainly a necessary move for all companies eventually, but there is a cost of going from one gate oxide material to another. Intel's 32nm is a second-generation high-k, which means their current 45nm recipe lasts only one generation, whereas SiO2 lasted how long. Not an easy issue to deal with. | Comment by GUEST on 2007-10-26 14:46:56
I would tend to agree - the HiK and SOI will not give the same benefit at 45nm. Just doing SOI is much cheaper than the HiK process Intel is using - I'm sure they would have gone that route if they were the same end product (performance/leakage).
No - HiK will be vastly superior to the AMD 45nm process. Even if AMD manages a volume ramp in 1H08 (which is unlikely) - their process will not be nearly as good from a performace standpoint.
It will be tough to compete in this scenario. | Comment by GUEST on 2007-10-25 15:47:21
It is clear you lack some understanding of ASML's volume orders compared to AMD's volume manufacturing. Just how many immersion litho tools do you think AMD need for a SINGLE factory (assuming immersion is only used on the 4 critical litho layers). Now factor in that the fab will not be built out on 45nm by end of 2008 (it will be maybe 1/4? 1/3?), and just how many tools do you think they will need?
Your attempt to associate AMD's ramp with ASML's volume tool orders comment is, with all due respect, lacking - AMD is a PITTANCE of ASML's tool orders and thus it should be fairly easy to reconcile the two seemingly incongruent statements.
Your attempt to correct your initial mistake with 'well I meant volume for AMD , which is 2009' (paraphrasing) shows that you still do not understand your error.
Oh and your comment on SOI enabling AMD to push out high K is laughable! High K is/was pushed out because IBM/AMD is not ready to do this in volume on 45nm. AMD is projecting a modest ~20% performance gain with 45nm - with high K they easily would have been able to obtain the traditional 30-40% gain typically targetted between nodes. To imply that AMD is making a willful decision to delay to 32nm is rather humorous.
10 months or more leadtime on state-of-the-art litho tools? Not quite - try MUCH LONGER! Unless "more" means 6+ additional months, your estimates are also way off here.
And did AMD say production in H1'08 or ramp in H1'08 (AMD could be using the word ramp to mean simply installing/qualifying equipment to get things in place for actual wafer outs in mid-2008). You have to be careful with AMD's statements these days - they parse their words very carefully (in an attempt to confuse folks like yourself). |
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October 2007 
