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Germanium-free strained SOI wafers |
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Feb 04, 2005 at 07:00 PM |
 Product Briefing Outline: Soitec has announced the
industry's first germanium-free, strained SOI solution for
partially-depleted CMOS IC architectures. Signaling a major step
forward in the strained silicon revolution, Soitec's scientific
advancement-enabled by the company's patented Smart Cut technology-will
allow chipmakers to achieve up to an 80-percent improvement in the
electron mobility of their future chips.
Problem: Improving device performance through carrier mobility
enhancements is one of the main issues in the industry today-yet until
now, a thick, germanium-free strained silicon technology did not exist
for partiallydepleted (PD) films used in the majority of leading-edge
chips. Soitec's new PD-sSOI fills this void, resulting in a thick 40-nm
strained silicon layer that exhibits excellent thickness and strain
uniformity across the entire wafer. Importantly it is claimed that this
high-level strain can be maintained throughout the subsequent
high-temperature processes used in the semiconductor manufacturing
cycle.
Solution: A strong advantage of sSOI substrates is that the mobility
enhancement factor is built into the substrate, thus spreading the
"strain" benefits to all regions of the integrated circuit and to all
transistor geometries. And, since wafer-level strain is now no longer
dependent on IC design, sSOI substrates will enable a wider range of
high-speed, low-power IC applications, including those with
high-performance logic cores. Most importantly, performance
improvements can be gained without significant process changes, or any
of the yield concerns associated with germanium-based strained SOI
technologies.
Applications: Both high-speed and low-power IC devices aimed at the
65nm node and below. Platform: With the addition of its new PD-sSOI
technology, Soitec will offer a complete portfolio of strained SOI
engineered substrates that are highly compatible with existing SOI
technologies and can meet a broad range of requirements for both
partially-depleted (>35 nm thick) and fully-depleted (<25 nm
thick) architectures.
Availability: October 2004 onwards.
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Product Briefings 
