The SOI Industry
Consortium has made available the first chapters of its
"SOI Implementation Guide," which features a series
of white papers and presentations from industry experts on specific topics to
promote a common understanding of the value and challenges of silicon-on-insulator (SOI) technologies.
The guide features subjects such as a methodology for comparing bulk and SOI process technologies for design teams investigating the potential benefits of engineered substrates, while another chapter deals with the advantages of partially depleted SOI circuit design, such as improved chip performance and lower power consumption, as well as the design issues raised by the bulk CMOS circuit design community.
Other upcoming chapters will include an SOI overview and analog and mixed-signal assessments (including six individual chapters on the application of SOI to RF and analog), SOI cost analysis, FinFets and SOI, and SRAM scalability in bulk and SOI, followed by a guide on how to port IP from bulk to SOI.
Certain chapters of the guide will initially be available to members only; the rest will be available to the general public on the consortium’s Website.
"Education is key to reducing barriers to adoption. Having easily accessible information is essential to providing the knowledge and expertise needed to inform the industry and eliminating present misconceptions," said Horacio Mendez, executive director of the consortium. "The ongoing creation of chapters for the 'SOI Implementation Guide' represents great teamwork and individual contributions from the companies and academic and R&D organizations within our consortium."
Members of the SOI consortium include AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Nvidia, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Symmid Semiconductor, Synopsys, TSMC, Tyndall Institute, UCL (Université Catholique de Louvain), and UMC.