Online information source for semiconductor professionals

A Novel Dual-Damascene ETCH Process Utilising a High-Selectivity, Ultralow-k Dielectric

01 March 2000 | By Mark Osborne | White Papers > Edition 11, Wafer Processing

Popular articles

Micron moving fast on Hynix in Q208 NAND flash rankings, says iSuppli - 19 August 2008

Numonyx to close California Technology Center - 12 August 2008

Qimonda starts major reorganization: exits PC DRAM market - 13 October 2008

Applied Materials sees higher CapEx spending for 2009 - 15 August 2008

Micron close to Inotera share purchase, says Gartner - 06 October 2008

TOM ROSENMAYER, JOHN BARTZ, SHICHUN QU & PING XU, W. L. Gore & Associates, Inc., Eau Claire, WI, USA

ABSTRACT

This article describes a potential dual-damascene etch process for an ultralow-k dielectric consisting of a nanocomposite of polytetrafluoroethylene (PTFE) and siloxane. PTFE has a high etch selectivity relative to common process materials. Trials of an integration scheme using this type of dielectric are described.

Please login to download the paper. No account yet? Please register. It's free!

Related jobs

Factory Start Up Director/Manager (Solar Factory Operations) - Applied Materials - , 07 August 2008

Quality Assurance Engineer - Tokyo Electron Limited - Santa Clara , 30 October 2007

Analog Design Engineer - AMI Semiconductor - Sunnyvale, 10 August 2007

Electrical engineering - Axcelis - Beverly, 10 August 2007

Senior Applications Engineer - Axcelis - Beverly, 09 August 2007

A Breakthrough in Low-k Barrier/Etch Stop Films for Copper Damascene Applications - 01 March 2000

IMEC reduces high-k/metal gate process steps from 15 to 9 - 17 June 2008

In Situ Single Chamber Processing: A Proven Capability for Dielectric Etch Processes - 01 March 2002

Copper interconnects with CVD low-k BEOL dielectric and their reliability - 01 March 2005