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Physical simulation predicts electrical circuit performance |
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Feb 04, 2005 at 09:00 PM |
 Product Briefing Outline: HPL Technologies has announced the
availability of Cell Designer, a next-generation DFM (Design for
Manufacturing) software solution targeted at devices built in advanced process technologies (130nm and below).
Problem: Traditional methods for yield improvement have relied on
internal efforts or long and expensive consulting engagements. These
approaches are not scalable and result in little internal yield
learning at high cost. Today, semiconductor manufacturers are demanding
a more scalable, software-oriented approach which truly brings
manufacturing issues to the designer's desktop. Cell Designer is the
first tool to effectively bridge the gap between the constraints of
semiconductor manufacturing
and the circuit performance requirements of design.
Solution: Cell Designer is the first tool to address the core issue of
DFM: predicting the electrical performance of a silicon circuit
manufactured in a specific process. Design data, such as circuit
netlist and layout, are combined with process information by physical
simulation to predict electrical circuit performance. Calibrated
process simulation accurately incorporates the effects of lithography,
etch, and process variation to obtain physical estimates for circuit
performance and yield. Cell Designer links for the first time design
and manufacturing to predict circuit electrical performance across
process variation in a fully integrated, easy-to-use package.
Applications: 130nm designs and below. Platform: Cell Designer was
developed through an agreement with SEQUOIA Design Systems, Inc., a
leading provider of physical simulation software for the semiconductor
manufacturing and design industry.
Availability: October 2004 onwards.
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Product Briefings 
