Problem: As designs continue to push toward faster speeds and smaller linewidths (65, 45, 32 and 22nm), the dielectric constant (k) required at each successive technology node is projected to continue dropping toward effective k-values of 2.5 or below.  Currently for integration schemes focused at the 65 and/or 45 nm technology nodes, many chip manufacturers have incorporated a film stack for their back-end-of-line (BEOL) process which includes Ta/TaN as the barrier metal, TEOS as a cap or hard mask, and low-k films such as BD-1, Coral or SiCOH.  During barrier polish, most customers remove the Ta/TaN barrier layer, polish through the TEOS and remove 200A or more of the low-k film. Device manufacturers are particularly concerned about achieving a very uniform final dielectric thickness across the wafer.  Additionally, device manufacturers prefer low and tunable low-K polishing rates to ensure that dielectric thickness does not degrade substantially during overpolish conditions necessary in manufacturing to hit final metal loss targets. Many barrier slurries currently on the market are capable of delivering high Ta/TaN and TEOS rates, but suffer from the required level of low-k control mentioned earlier.  As a result, customers have reported unacceptable levels of Rs variation, under conditions of overpolish, due to the variability in copper to dielectric selectivity. 

Solution: Cabot Microelectronics has performed an extensive study of the various low-K films -- currently -- in use to better understand how to develop tailored slurry formulations that meet our customer's needs for consistent electrical performance and manufacturing robustness.  In studies, Cabot have discovered there is significant variation in the incoming surface energy associated with the various low-k films used in industry due to differences in the carbon content.  Cabot Microelectronics has also identified that there is significant variation in these energetics even within a specific type of low-k film.  In order to fully control the variation in the surface structure it is necessary to reduce the molecular level variation seen at the low K interface.  To address these challenges, CMC has developed a low-k rate control strategy which utilizes specific chemistries that selectively adsorb to the low K surface and inhibit the removal rate on both the hydrophilic (Si-O) and hydrophobic (Si-O-C) portions of the film. The B6600 barrier slurries can now be designed to provide optimal electrical performance in low-k applications (either with capped or uncapped film stacks).

Applications: Copper Barrier/ low-k CMP at the 65nm-45nm nodes.

Platform: B6600 barrier slurries use a low-k rate control strategy which utilizes specific chemistries that selectively adsorb to the low K surface and inhibit the removal rate on both the hydrophilic (Si-O) and hydrophobic (Si-O-C) portions of the film. The addition of the multi-component low K control chemistry has shown a significant improvement on the overall Rs non-uniformity even as a function of over-polish.

Availability: July 2007 onwards.

Figure 1: is a schematic representation of the pre and post CMP film stacks used at the 65nm and 45nm nodes.

Figure 2:  Surface response map showing degree of low K surface structure variation.

Figure 3:  Schematic representation of selective molecule adsorption for low K rate control.