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Home arrow News arrow Wafer Processing arrow TSMC’s 130nm embedded flash technology uses copper & DFT
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TSMC’s 130nm embedded flash technology uses copper & DFT Print E-mail
Aug 21, 2007 at 12:47 PM
ImageTSMC has announced that its recently qualified fully logic-compatible 130nm process featuring embedded flash technology comes with copper wiring for the first time, making it ideal for ultra-low power applications.

"The process's low power transistor makes it ideal for ZigBee/Wibree devices, wireless headsets, hearing aids, SmartCards and other applications requiring ultra low power consumption ranging from 1.2V to 1.5V," stated Sam Chen, Director of memory platform marketing at TSMC. "And the value of this process can be further enhanced by TSMC's comprehensive and cost-effective embedded flash IP testing support."

TSMC has also added a "design for test (DFT)" module that maximizes the numbers of die tested in one single test in an effort to control escalating test costs. According to TSMC, designers can now choose either Multiplexing (MUX) or a Serial scheme,
depending on their need for ease of implementation or low pin count.
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