Mark E. Mason, Texas Instruments Incorporated, Dallas, Texas, USA

ABSTRACT

In 1965, Gordon Moore set a path for lithographers that has led directly to the abundant use of resolution enhancement technologies (RETs) for patterning semiconductor devices. Not surprisingly, these RETs have a real cost in terms of computation times, complexity, license fees, and support manpower. The International Sematech Cost of Ownership (CoO) analysis [1] can be extended to estimate the impact of RETs on overall lithography CoO and on the cost per modern semiconductor wafer, which appears to be around $10/RET level for a high-volume ASIC case.