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9th Edition:Benchmarking Wafer Fabrication Process Tool Hook-up A Proposed Standard Methodology Print E-mail
Nov 04, 1998 at 11:14 AM

A. WELLS, Siemens Microelectronics Ltd., Newcastle on Tyne, UK

As time to market and product life cycles become progressively shorter, ref [1], the focus on a fast tool Hook-up to provide an opportunity for early first silicon is becoming even more critical. With a depressed semiconductor market situation however, the reduction of capital expenditure is the primary focus, ref [2]. The goal of this article is to understand the underlying processes involved in Hook-up and optimise them to provide the "best practice", lowest cost and time solution. The article will also disprove the current paradigm that high speed necessarily means high cost, and the following text summarises the method for the much more detailed study undertaken this year.

9th Edition: Benchmarking Wafer Fabrication Process Tool Hook-up A Proposed Standard Methodology for the Industry
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