By Dr Mike Cooke
Keithley Instruments has entered into a Joint Development Partnership (JDP) to advance semiconductor device material testing technology with the French CEA Leti research centre. The JDP calls for Keithley and CEA Leti to research methods for characterizing advanced semiconductor materials and devices that support DC, high frequency and RF-level signals on both micro- and nano-level structures.

CEA Leti will use Keithley RF-enabled semiconductor test equipment as part of its research projects in order to expand and enhance understanding of the performance of semiconductor devices that perform at the highest levels.

"The ability to make high quality electrical measurements is crucial to advance the [European] ‘More Moore' and ‘More Than Moore' initiatives forward," explained Olivier Demolliens, head of the Nanotech Division at CEA Leti. "Our electrical experts need the finest data to understand, model, and improve our devices."

CEA Leti has recently opened a new innovation center called MINATEC. CEA Leti is one of the main drivers behind the formation of MINATEC, which will function as Europe's main Centre of Excellence in micro- and nano-technology, bringing together more than 4000 researchers, industrialists, and teaching staff in Grenoble, France. CEA Leti reports that MINATEC will focus the activities of researchers, teachers, and manufacturers working in micro- and nano-technologies on a single campus and allow the development of joint initiatives.
Keithley specializes in parametric test to enable measurements at key stages in the wafer process. Its Model 4200-SCS Semiconductor Characterization System performs pulse testing of miniaturized and fragile devices. The Model 4200-SCS is a lab-based system that incorporates tightly integrated DC and pulse measurement capabilities with complete application packages for turn-key solutions. The Model 4200-SCS Pulse I-V package supplies instrumentation, connections, and software that allow semiconductor engineers to take ultra-short pulse measurements at the transistor level while they are still on an integrated circuit wafer.