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Cadence teams with STARC on 65nm DFM issues |
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Jul 11, 2007 at 04:45 PM |
 Cadence Design Systems follows a long line of EDA and DFM companies collaborating with Japan's Semiconductor Technology Academic Research Center (STARC) member companies. The design company has employed an advanced design flow to improve manufacturability and yield for 65nm designs developed at STARC. Cadence said they have been collaborating with STARC for over 15 months to provide member companies with a new set of DFM capabilities.
"Through our collaboration with Cadence, we believe we can help our member companies address their most pressing DFM issues at 65 nanometers," said Nobuyuki Nishiguchi, Vice President and General Manager of Development Dept.-1 at STARC. "Because the flow is based on the integration of key DFM technologies into the Encounter platform, our member companies will be able to improve yield while still meeting aggressive power, performance and schedule requirements."
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