Online information source for semiconductor professionals

Product Briefing Outline: VLSI Standards, Inc. has announced the release of its Edge Contamination Standards (ECS) product line. These NIST-traceable calibration standards will allow users to calibrate, characterize and monitor Scanning Surface Inspection Systems (SSIS) that detect and size particles on the substrate's edge.

Problem: More and more semiconductor manufacturers are adopting the use of Edge Detection Inspection Systems as part of their overall defect yield strategy.  This increases the amount of the total wafer surface that will be inspected by 5-7 percent. To date, there has been no way for users to perform calibration and system monitoring of these advanced edge detection tools for sensitivity and accuracy.

Solution: Available for the first time in the industry, VLSI Standards' solution for edge contamination metrology utilizes precise deposition of polystyrene latex spheres (PSL) onto four distinct regions on the substrate's edge.  The PSL spheres deposited on the ECS are highly spherical, have well-characterized optical properties and a very tight monodisperse size distribution.  Each deposition area covers the top and bottom near edges, the top and bottom wafer bevels, and the apex or true edge of the wafer (see below).  This allows the user to perform both topside and backside inspections to check the complete sensitivity of the tool.

Applications: The Edge Contamination Standards are used to calibrate and monitor any Scanning Surface Inspection Systems, which have the capability of scanning the edge of substrates for particle count and size.

Platform: These standards come with nominal 0.5µm, 1.0µm, 2.0µm and 5.0µm PSL sizes deposited on the edge of a silicon wafer.  Approximately a few thousand particles are located in each deposited region. The ECSs are available in both 200mm and 300mm wafer diameter versions. All standards come with a NIST Traceable Certificate of Calibration.

Availability: July 2007 onwards.