|
Fujitsu aims millisecond annealing technique and porous low-k for 45nm intro |
|
|
|
Jun 18, 2007 at 05:56 PM |
 Fujitsu Limited and Fujitsu Laboratories are claiming that its 45nm process technology due for introduction in 2008 will reduce interconnect-induced lag times by approximately 14 percent.
Fujitsu researchers have used nano-clustering silica (NCS), which has a dielectric constant (k) of 2.25. NCS is an insulating material pocked with miniscule holes, enabling both a low dielectric value and high mechanical strength, according to the company.
Fujitsu said that they had introduced NCS on a partial basis beginning with the 65nm generation. However, for the 45nm generation, the company will use NCS within a given interconnect layer but also between different layers to further reduce interconnect capacitance.
Millisecond annealing will be used to limit transistor resistance, reducing leakage current to one-fifth that of previous levels, Fujitsu claims.
Details of the new technology were presented at the 2007 Symposium on VLSI Technology.
|
News 
