Online information source for semiconductor professionals

Product Briefing Outline: Sagantec has launched a DFM solution for correcting lithography hot spots found in physical IC designs in collaboration with Mentor Graphics. The new DFM flow uses Mentor Graphics' ‘Calibre LFD' (litho friendly design) tool to analyze the design layout and detect lithography hot spots. Sagantec's DFM-Fix tool uses the Calibre LFD analysis results to correct hot spots and optimize the overall layout, which is then verified by Calibre LFD. Sagantec claims that DFM-Fix is the first product that solves the lithography-related "hot spot" problem at the root, by correcting the design data.

Problem: In previous technology generations, DFM was implemented by design rules. A design rule clean tape-out meant delay-free mask preparation, and error-free silicon manufacturing. At 65nm and beyond, design rules are no longer sufficient for predictable manufacturability. Due to lithography issues and increased process variability, certain patterns that are DRC correct might not print properly on a wafer, resulting in severe yield degradation.

Solution: DFM-Fix uses information generated by lithography analysis to identify hot spots and correct them in the physical design database. DFM-Fix corrects the physical shapes with minimal impact on the design and without violating design rules. At the core of the product is a hierarchical layout optimization engine that makes subtle polygon movements at minimum design-rule increments, and maintains design rule check (DRC) correctness while performing model-based optimization. Compared to other correction methods, DFM-Fix can move and size any wire, edge and shape to any location, size and width while maintaining complete DRC correctness of all related polygons across all relevant layers and hierarchy levels.

Applications: 65nm designs and below.

Platform: At the core of the product is a hierarchical layout compaction and optimization engine developed on the basis of Sagantec's SiFix. This layout optimization technology can make subtle polygon movements at minimum design-rule increments, and maintain design rule check (DRC) correctness while performing model-based optimization. The advantages of compaction compared to other methods is that it can move and size any wire and shape to any location and width while maintaining complete DRC correctness of all related polygons across all relevant layers.

Availability: June 2007 onwards.