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PETER M. ZEITZOFF, SEMATECH Inc., Austin, TX, USA

ABSTRACT

The 1997 version of the National Technology Roadmap for Semiconductors, (NTRS), ref [1], assumes the continuation of Moore’s Law type scaling for mainstream CMOS technology for the next fifteen years. For the 180 through the 100 nm technology generations, key trends are continued sharp scaling of Vdd and device dimensions such as gate oxide thickness, junction depths, gate length, contact and metal layer minimum dimensions, etc., while the threshold voltage remains approximately constant. The device drive current and off current are remaining approximately constant while the maximum chip operating frequency and the overall chip power dissipation are increasing. Key issues include gate leakage, oxide reliability, and boron penetration for 2.0 nm and less equivalent oxide thickness, polysilicon gate depletion effects, the nonscalability of threshold voltage, and fabrication of very shallow source/drain extensions. Potential solutions include the use of alternate high K gate dielectrics and metal gate electrodes, use of very low energy implantation, use of sophisticated channel doping techniques such as super steep retrograde profiles and pocket implants, and use of alternate silicides.