Home
News
Blogs
Fabtech Jobs
Product Briefings
Going Places
300mm Activity Reports
Core Sections
Wafer Processing
Lithography
Fab management
Materials & Gases
Critical Components
Cleanroom
EHS
 
Find

GlobalSpec - The Engineering Search Engine
 
Home arrow Lithography arrow News arrow Lithography arrow STARC to use Brion’s DFM workflow solutions for 65nm designs
STARC to use Brion’s DFM workflow solutions for 65nm designs Print E-mail
May 24, 2007 at 04:48 PM
BrionBrion Technologies, an ASML company, has said that it is collaborating with 11 member companies of the Japanese Semiconductor Technology Academic Research Center (STARC) to develop and test a complete DFM workflow solution for 65nm devices planned for production.

"Working with Brion and its EDA partners is a natural next step for STARC, as we continue our mission of delivering proven methodologies to our member companies," said Nobuyuki Nishiguchi, vice president, general manager, development department-1 of STARC. "Most of STARC's member companies are already Brion customers and Tachyon users. They naturally want to use the same accurate, production-qualified lithography models created by Tachyon along their entire process flows, from design to mask making to manufacturing."

"Having a lithography-aware design flow that correlates well to both mask making and device production is essential at the 65nm node and beyond," said Shauh-Teh Juang, Brion's senior vice president of marketing and business development. "Multiple and inaccurate models can be avoided. Furthermore, incorporating computational lithography into the entire production flow can optimize runtime and mask costs while minimizing variability in the device design at each stage, from design verification to production. We're very pleased to be working with STARC, helping bring lithography-aware DFM to their members' design and production flows."
 
STARC has collaborated previously with a wide range of DFM suppliers.
Readers' comments



Bookmark with:
DeliciousDiggredditStumbleUpon

Visit Fabtech Jobs websiteSubscribe to Fabtech weekly newsletter

Related articles
STARC adds Blaze DFM’s Halo product to 65nm design implementation  (03/08/2007)
Cadence teams with STARC on 65nm DFM issues  (11/07/2007)
Japan’s STARC center selects Blaze DFM for leakage power optimization  (24/01/2007)
Tool Order: Japanese chip manufacturer to use Brion's Tachyon OPC+ for 65nm  (04/10/2006)
Tool Order: Crolles2 Alliance extends DFM work with Brion to 45nm node  (06/06/2006)

Related jobs
Manager, Facilities and Support Services  (PERRYSBURG, 19/03/2008)
Senior Component Design Engineer  (Intel Shannon, Co Clare, Ireland, 19/03/2008)
Software Engineer  (Santa Clara, 09/08/2007)
Algorithm Development Engineer  (Santa Clara, 09/08/2007)
Senior Algorithm Development Engineer  (Santa Clara, 09/08/2007)
Subscribe
300mm