Ingrid B. Peterson, KLA-Tencor Corporation, Milpitas, CA, USA

One of the challenges facing the implementation of DUV and advanced i-line lithography processes in production is that of maintaining low defect density in order to minimize the impact on yield. Yield depends on the complex interaction between design, CD and overlay control, films, electrical parameters, and defects. As the geometries shrink and the chip size increases, defect reduction becomes increasingly important.