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Kawasaki migrates ASIC chip to TSMC’s 90nm eDRAM process |
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May 09, 2007 at 03:30 PM |
 Kawasaki Microelectronics (K-micro) has claimed that its successful migration of a digital TV ASIC chip to TSMC's 90nm embedded DRAM process has proved that processing difficulties such as gate leakage and cell capacitance at these feature sizes have been overcome. The process has been in production since the first quarter of 2006, according to the company.
"K-micro's adoption of the TSMC 90nm eDRAM process for DTV application signifies a milestone in our technology development, manifesting that we have successfully overcome historic eDRAM process difficulties such as pass gate leakage, cell capacitance, and stacked contact without compromising cost effectiveness," said Dr. Kenneth Kin, senior VP of worldwide sales and service at TSMC. "K-micro's production exemplifies the win-win synergy that is the hallmark of our customer partnerships."
The 90nm embedded DRAM process is CMOS logic-based and incorporates an add-on memory module. The embedded process eliminates I/O power consumed interfacing with external DRAM devices, and provides a wider bus while lowering material costs. The process is claimed to consume less active and standby power than a typical SRAM device and features a 60 percent smaller macro size, according to TSMC.
K-micro has been using TSMC as one of its foundry partners since 2002.
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