Reza Arghavani, Hichem M'Saad, Ellie Yieh, Gary Miner & Satheesh Kuppurao, Applied Materials, California, & Scott E. Thompson, University of Florida

ABSTRACT

Historical device scaling has relied on gate length, gate dielectric and junction depth scaling to enhance performance. However, these conventional methods for device scaling have reached limits at the 90nm technology node with gate dielectrics being five atomic layers and junction depths being at ~10nm. Further scaling of either is not practical due to increased gate leakage currents or external resistance. Extrapolation of existing device trends shows significant barriers beyond the 45nm technology node. As a result, some semiconductor researchers have concluded that disruptive technologies such as vertical-transistor FinFETs or other exotic transistor architectures are required to achieve high-volume manufacturing at the 32nm node.