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Home arrow Wafer Processing arrow Articles arrow Edition 32 arrow 32nd Edition: Deep trench metrology challenges for 75nm DRA...
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32nd Edition: Deep trench metrology challenges for 75nm DRAM technology Print E-mail
Dec 20, 2006 at 04:06 PM

Peter Weidner, Alexander Kasic, Thomas Hingst & Thomas Lindner, Qimonda Dresden, Germany

ABSTRACT

The demand for new DRAM technologies with smaller ground rules leads to new challenges for inline metrology. This paper addresses inline monitoring of structural dimensions like depths and critical dimension (CD), excluding defect density monitoring and advanced process control techniques. Qimonda pursues the deep trench (DT) capacitor concept. A main module in DRAM manufacturing comprises DT etch, capacity enhancing steps, and the connection of the DT to the device. Interesting demands for metrology emerge with every new technology node. Focusing on 75nm DRAM technology, this paper will highlight key processes in the DT module. 

32nd Edition: Deep trench metrology challenges for 75nm DRAM technology
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