"Customers expect both performance and reliability from TSMC, a fact that has guided the development of our 45nm process every step of the way," said Dr. Rick Tsai, president and CEO of TSMC. "With our 45nm solution ready and production to be started in September, TSMC provides next-generation technology at the earliest possible time."

Key to TSMC's ability to match Intel's plans to migrate to the 45nm node before the end of the year is the continued use of strain-engineering techniques and a second generation low-k dielectric for interconnects dubbed ‘extreme low-k' (ELK) by TSMC.

TSMC has not adopted a high-k dielectric or metal gates at the 45nm, making qualification easier and processes less complicated.

Previously, TSMC would lag major chip manufacturers' technology node migrations by approximately 12 months, but it would seem that at the 45nm node TSMC has significantly closed the gap, albeit with a less advanced process compared to Intel or AMD and IBM, which use SOI wafers and strain-engineering techniques. TSMC is still committed to bulk CMOS at the 45nm node.

As expected, TSMC will use 193nm ArF immersion lithography for the first time across process platforms starting at the 45nm node. ASML is TSMC's sole supplier of DUV lithography tools.

TSMC's first 45nm ‘CyberShuttle' has produced working die, according to the company, with a double-digit number of companies in various stages of CyberShuttle testing.

"Our customers' enthusiasm for the 45nm CyberShuttle is an auspicious leading indicator of the success of TSMC's 45nm process," said Dr. Rick Tsai, president and CEO of TSMC. "We are marshalling the full resources of our design ecosystem to support our 45nm process and respond to the anticipated demand."

TSMC also said that a full range of design support services for its 45nm process were now in place and further CyberShuttles were arranged for May, August and December.