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11th Edition: Wafer Backside Spin-Process Contamination Elimination for Advanced Copper Devices |
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Feb 03, 2005 at 04:17 PM |
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ERNST GAULHOFER & HEINZ OYRER, SEZ A.G, Austria
BING-YUE TSUI, National Chiao Tung University, Hsinchu, Taiwan ABSTRACT
Wafer
cleaning is the most frequently repeated process in semiconductor
manufacturing and with an industry-wide move to copper interconnects,
contamination control requirements are extremely critical. Interconnect
delay begins to dominate overall device delay at 0.18µm, making
lowresistance copper attractive and a highly reliable cleaning process
becomes essential, especially considering the expense of frequent
contamination monitoring. Successful integration requires stringent
control of cross contamination from deposition equipment (PVD, CVD, and
electroplating tools), CMP equipment, and all metrology tools shared by
copper processed wafers
Additionally, the exclusion zone on the
front-side of the wafer is another source of cross contamination.
Semiconductor wafer fabrication companies insist on a method that
utilises existing equipment for development of copper applications.
Therefore, a highly effective method of eliminating copper from the
wafer backside, bevel and edge must be implemented. The combination of
edge cleaning and the edge evaluation is available for introducing not
only Cu but new exotic materials such as Ta2O5, BST and Ruthenium too.
 Wafer Backside Spin-Process Contamination Elimination for Advanced Copper Device Applications
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Wafer Processing 