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Home arrow Wafer Processing arrow Articles arrow Edition 11 arrow 11th Edition: Challenges in Copper Interconnect Technology:...
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11th Edition: Challenges in Copper Interconnect Technology: Macro-Uniformity and Micro-Filling Power Print E-mail
Feb 03, 2005 at 04:08 PM

JACOB JORNE, Cupricon Inc., Rochester, NY, USA

ABSTRACT

The main challenges facing the electroplating of copper on wafers for interconnection are uniformity and conformity. The difference between these two requirements is due to the scales involved. Uniformity over the entire wafer involves the scale of up to 30 cm, while the conformity and the filling ability of trenches and vias involve the scale of sub-micron. This difference requires clarification, as the traditional concept of throwing power is not applicable here. The non-uniformity of copper plating is due to the appreciable resistance of the thin barrier and seed layers and depends also on the geometry of the electroplating system

The macro-distribution depends on the ratio of the electronic resistance of the thin copper seed layer to the electrochemical resistance. A dimensionless parameter B, which determines the uniformity of the deposit, is identified as the ratio between the resistance of the thin copper layer and the resistance of the electrolyte plus the electrochemical reaction. When the current is fed to the periphery of the wafer, the copper layer is thicker there and thinner at the centre of the wafer. Nonuniformity in copper plating is expected to be more severe for large wafers (200mm). Methods to improve the uniformity of the copper deposit include the usage of low conductivity electrolyte and the presence of organic additives in the electrolyte.
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