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Samsung preps 3D DRAM transistor for 2008 production |
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Oct 19, 2006 at 06:50 PM |
 Samsung Electronics plans to use a three-dimensional (3D) transistor design, multi-layered dielectrics and recessed channel array transistor (RCAT) technology in its 50nm DRAM devices due to enter volume production in 2008.
"With the 50nm DRAM development, we're continuing our technology leadership, paving the way for our customers to reap not only greater cost efficiencies but also to make superior products," said Nam Yong Cho, executive vice president of memory sales & marketing at Samsung Electronics' Semiconductor business.
The 3D transistor will employ a selective epitaxial growth transistor (SEG Tr) that has a broader electron channel, optimizing the speed of each chip's electrons to reduce power consumption and enable higher performance, according to the company. The SEG transistor introduces a multi-layered dielectric layer (ZrO2/Al2O3/ZrO2) to resolve weak electrical features. In addition, the new dielectric layer sustains higher volumes of electron to increase storage capacity.
As with its 70nm design (see image), Samsung will use its RCAT technology to increase Leff by recessing the channel from the silicon surface. This in turn reduces leakage and boost data storage characteristics.
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