Home
News
Blogs
Fabtech Jobs
Product Briefings
Going Places
300mm Activity Reports
Core Sections
Wafer Processing
Lithography
Fab management
Materials & Gases
Critical Components
Cleanroom
EHS
 
Find

GlobalSpec - The Engineering Search Engine
 
Home arrow Wafer Processing arrow Articles arrow Edition 12 arrow 12th Edition: High k Dielectrics for Advanced Dram Applicat...
Flash Banner
12th Edition: High k Dielectrics for Advanced Dram Applications Print E-mail
Feb 03, 2005 at 12:01 PM

VISWESWAREN SIVARAMAKRISHNAN, PRAVIN NARWANKAR, HELEN ARMER, PATRICIA LIU, JUN ZHAO & RAVI RAJAGOPALAN, Applied Materials, Inc., Santa Clara, CA, USA

ABSTRACT

Gigabit DRAMs will be fabricated with feature sizes <0.13 µm, with cell size equal to 0.14 µm2 and capacitor area equal to 0.051 µm2. These require alternative high k dielectric materials in place of silicon oxide and silicon nitride. The most promising high k dielectric candidate for sub-0.13 µm design rule devices is tantalum pentoxide (Ta2O5). This article discusses issues associated with implementing high k dielectric solutions, including Ta2O5 dielectric deposition, remote plasma oxidation and crystallisation of the Ta2O5, TiN top electrode formation, nitridation of polysilicon, and production worthiness issues of the process.<


icon High k Dielectrics for Advanced Dram Applications

Readers' comments



Bookmark with:
DeliciousDiggredditStumbleUpon

Visit Fabtech Jobs websiteSubscribe to Fabtech weekly newsletter

Related articles
10th Edition: A New CVD Process For Damascene Low k Applications  (04/02/2005)
11th Edition: Low-k Dielectrics for Future IC Fabrication  (03/02/2005)
14th Edition: Dry Etching of High-k Materials for Future Memory Applications  (03/02/2005)
19th Edition: Scaling plasma-nitrided dielectrics to the 65-nm node  (21/01/2005)
19th Edition: DRAM technology for 100 nm and beyond  (20/01/2005)

Related jobs
Concept Engineer - IO Simulation Support, Qimonda Japan  (, 17/10/2007)
Layout Engineer  (Cary, 15/10/2007)
DRAM - Development Center - Product Verification  (, 14/10/2007)
Layout Engineer  (Cary, 15/08/2007)
Design Engineer  (Williston, 15/08/2007)