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Reliability and packaging verification of Cu/low-k interconnects for

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Wilbur Catabay, Advanced Process Module Development, LSI Logic Corporation, Stan Mihelcic, Advanced Packaging Solutions, LSI Logic Corporation, Jennifer Sabharwal, Deenesh Padhi, Li-Qun Xia & Tony Pan, Applied Materials, Incorporated.

ABSTRACT

After more than five years of extensive development, chipmakers worldwide have finally entered volume manufacturing with low-k dielectrics producing the most advanced 130-nm copper interconnect devices available in the market today. Although several low-k materials exist, IC manufacturers are predominately using the CVD carbon doped oxide (CDO) film called Black Diamond®, developed by Applied Materials. This article explores the key considerations, parameters and obstacles faced during the implementation of low-k dielectrics into volume production and describes how these inter-related challenges were overcome to achieve successful integration of multi-metal devices while attaining good wafer level and package level reliability. It also examines implementation of the Black Diamond film by a leading chipmaker, LSI Logic, who currently offers a low-k /Cu integration scheme in its Gflx™ 110-nm process technology for both cell-based ASIC and its innovative RapidChip™ Platform ASIC designs.

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