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New Product: PDF Solutions upgrades parametric yield analysis of analog and RF IC designs |
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Oct 10, 2006 at 03:05 PM |
 Product Briefing Outline: PDF Solutions Inc. has introduced a new release of its ‘Circuit Surfer' software for characterizing and optimizing the parametric yield of analog and radio frequency (RF) integrated circuit (IC) designs. The new release features the company's patented mismatch simulation technology, which helps to minimize the number of simulations required to characterize parametric yield. It is also claimed to reduce design re-spins by identifying parametric yield loss mechanisms not visible when using verification methods based on corner modeling.
Problem: Most design-for-manufacturing (DFM) and design-for-yield (DFY) software tools for circuit simulation suffer from the well-known limitations of Monte Carlo-based analyses: the number of circuit simulations required to quantify yield and the trade-offs with respect to the device areas to optimize performance and manufacturability. The greater the number of simulations, the longer it takes to accurately quantify yield, thus affecting overall verification times, time-to-market, and time-to-profit. Device mismatch is the dominant form of parametric yield loss today in much of the custom IP used in ICs. From an IC schematic and layout perspective, designers typically are aware of which devices should be matched, but it is often unclear how much each of the matched sets of devices will affect circuit output variability. This is especially true for larger circuits with many matched sets of devices. Other than through direct current (DC) analyses, existing electronic design automation (EDA) tools do not make apparent to designers how mismatch will affect alternating current (AC), transient, and RF performance. Therefore, reducing the effects of mismatch typically results in creating unnecessarily larger area devices, which inherently makes non-beneficial trade-offs in layout area, power, and other chip traits.
Solution: Circuit Surfer is designed to alleviate long design cycles by reducing the total number of circuit simulations — by 10x to 100x — needed to obtain an accurate analysis of a chip's predicted performance and parametric yield. The parametric analysis capabilities in Circuit Surfer quickly identify, verify, and quantify for designers all of the critical individual process and device sensitivities, as well as pairs of matched devices and their contributions to the output variability. This shows designers which devices to focus on for both performance and yield improvement.
Applications: Parametric yield of analog & RF integrated circuit designs.
Platform: The software is integrated into the Cadence Analog Design Environment (with Agilent RFDE) and is compatible with the Synopsys Hspice software.
Availability: October 2006 onwards
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