Emerging from the dual metal gate vs. FUSI panel discussion was the widely predominant view that FUSI presents more manufacturing concerns than the dual metal gate approach. While FUSI technology may seem attractive for some applications, most see it as having significant limitations in high-performance implementations and high-volume manufacturing, SEMATECH noted in a press release.

According to Symposium Chair Hsing-Huang Tseng, who also is SEMATECH FEP Division chief technologist and CMOS Extension program manager, the Symposium achieved its goal of improving consensus on strategies for high-k/metal gate stack implementation.

"It's clear that we need to work collaboratively on fundamental issues of materials science if we are to stay on the roadmap to scale CMOS transistors and achieve manufacturable results in the next decade," said Tseng. "The Symposium addressed many issues we're facing in the hybrid integration of heterogeneous materials, and the experts who attended were very interactive in promoting and in many cases reconciling their research findings."

In the area of dual work function metal gates, there is a growing consensus that nMOS metal gate electrode materials have now been identified, are yielding an effective work function close to that of doped polysilicon gates, and are no longer a critical issue. On the other hand, pMOS metals remain problematic, owing to threshold voltage roll-off in scaling the dielectric thickness. Symposium presentations by J. Schaeffer from Freescale and H.C. Wen of SEMATECH, among others, outlined these findings, SEMATECH noted.

Presentations by Y. Nara from Selete, who demonstrated dual workfunction full metal gate devices consisting of tungsten stacked on workfunction control metal layers, and by J. Robertson from Cambridge University, who described the fundamental mechanisms of defect passivation by fluorine, were representative of new findings that were announced for the first time at the Symposium.

According to SEMATECH, several speakers presented work being done on Ge and III-V
alternative channel material devices. Though progress is being made, there was general acknowledgement among Symposium attendees that this area of study will require more effort and more resources as manufacturable solutions have not yet been demonstrated.

The image shows a 50nm FUSI gate stack developed at IMEC.