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NEC supports litho-friendly design flow third party collaboration |
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Oct 03, 2006 at 02:21 PM |
 In an effort to tackle the complexities of interoperability between core EDA software and DFM software from third party specialists, Cadence Design Systems has been collaborating with NEC, Brion Technologies and Clear Shape Technologies to provide IC designers with a lithography-aware design flow with a defined interface that accurately links RET models with physical design and verification.
"As we implement advanced process flows, we see lithography impacts on design becoming more and more critical," said Shuichi Inoue, general manager, Process Technology Division at NEC Electronics Corporation. "As a customer of both Brion and Cadence, we're pleased to see this type of collaboration, which enables a lithography-aware design flow that correlates well to the mask-making and manufacturing stages. NEC Electronics will help to drive and to provide requirements and directions for this effort."
IC designers can now use the same models throughout the flow and into manufacturing, as advanced manufacturability models can now be used within the design phase.
"In keeping with our vision and plan to create a lithography-aware design and implementation flow targeted for challenges at 65 nanometers and below, we've defined an interface that links both internal and external lithography modeling and verification technologies with our design and implementation solutions," said Wei-Jin Dai, corporate vice president at Cadence. "This design flow is intended for customers who are designing at leading-edge 65-, 45-, and 32-nanometer processes and those developing lithography-aware DFM flows."
"Cadence and Brion have collaborated for months to define a lithography-aware design flow that enables our mutual customers to link signoff quality OPC and OPC verification with design stage layout optimizations," said Dr. Shauh-Teh Juang, senior vice president of marketing and business development at Brion Technologies. "With 12 of the top 15 semiconductor manufacturers using Brion for OPC or OPC verification, we are seeing the demand for this type of design flow which minimizes the risk of costly yield issues."
"At sub-90-nanometers the industry needs to move from ideal-GDSII based design to true silicon-accurate design" said Atul Sharan, CEO of Clear Shape Technologies. "Clear Shape has developed unique technologies that enable fast and accurate prediction of silicon in an OPC & RET tool-agnostic manner. Our goal is to put DFM solutions that analyze and account for systematic variations on designers' desktops. Linking our technologies with Cadence's widely deployed physical design and verification platforms provides designers with a plug-in solution that bridges design and manufacturing."
"The new lithography-aware design flow will allow ATI to link manufacturability and design implementation, providing an important element of our robust DFM strategy," said Greg Buchner, vice president of Engineering, ATI Technologies Inc. "By utilizing Cadence Chip Optimizer to automatically fix hot spots that are accurately predicted during our physical design phase by Clear Shape's InShape tool, we are able to prevent costly and time-consuming iterations that rely on detecting lithography problems after tape-out or, even worse, in silicon. We're encouraged by this type of collaboration and hope to see more situations of companies working together to help solve broader industry problems."
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