Although the IEEE International Electron Devices Meeting (IEDM) is not until December, IMEC have announced that it has a record number of papers accepted for presentation at one of the most important semiconductor processing conferences held each year.

Several advances will be reported in the scaling of logic technology options. For extending bulk CMOS into the 45/32nm nodes, IMEC has developed an alternate integration process for their FUSI technology that is more manufacturing friendly without the need for a CMP step. It is based on using a planarizing resist and etch-back to open the FUSI gates, according to the research centre.

New metal gate processes designed for manufacturability will also be reported, such as MoOx on the pFET. On FinFET's, IMEC  plans to demonstrate the impact of fin line-edge roughness on device characteristics, as well as the process technology to double or quadruple the fin density per area.

Beyond silicon as substrate, IMEC will demonstrate a short channel Ge pMOS device built with Si-compatible process techniques. IMEC will also report a new integration process for backside thinned CMOS imagers with increased performance.

NBTI (negative biased temperature instability) degradation experiments under AC conditions at frequencies up to 2GHz in SiON-based dielectrics will also be presented, emphasizing IMEC's work on reliability performance in advanced processes. It will also be shown that ultra-fast progressive breakdown in HfO2/TaN/TiN gate stacks n/p-MOSFETs only occurs during substrate injection. A model to explain this polarity dependence will be presented.

Papers on non-volatile memory will focus on reliability modeling. A model that allows describing the leakage current through high-k insulators, highlights the long-term retention time issues for new-generation Flash technologies that are expected to  incorporate high-k interpoly dielectrics as well as the possibility of using tunnel layers.

IMEC will also report a new integration process for backside thinned CMOS imagers with increased performance. Beyond silicon as substrate, IMEC will present on a short channel Ge pMOS device built with Si-compatible process techniques.