Problem: Below the 65nm node, 4x reticles for leading-edge chip designs have features smaller than the wavelength of light used in advanced exposure tools. These features cause significant scattering and polarization of the exposure light and must be accounted for to achieve accurate high numerical aperture (NA) lithography. Unlike conventional edge-based sampling methods, Tachyon uses a hybrid computational lithography architecture that combines image-based lithography process simulation and polygon-based data manipulation to simulate 100 percent of the chip area.

Solution: Tachyon M3D constructs image-based photomask imaging models using rigorous electromagnetic field simulation of the light passing through the 3D mask feature topography on 4x reticles. For high-speed, full-chip computational lithography, Tachyon M3D replaces the thin mask approximation with its image-based mask 3D models, then computes and combines wafer image intensities from different source polarizations, before resist and etch computations. Tachyon M3D's capabilities are also important when applied to through-focus lithography modeling because of the significant mask 3D effects that can occur across the full range of focus variation during the manufacturing process. These capabilities are critical to OPC and OPC verification of leading-edge semiconductor designs, since focus variation is inevitable, and becomes more severe as lithography process windows shrink with each successive technology node.

Applications: Sun-65nm OPC verification

Platform: With Tachyon M3D, wafer pattern distortions caused by mask 3D effects can be corrected by Tachyon OPC+ and verified by Tachyon LMC with a single FEM model.

Availability: September 2006 onwards