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Toshiba chooses Mentor Graphics’ Calibre DFM tools for 45nm node
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Toshiba Corporation has selected the Mentor Graphics ‘Calibre’ DFM
platform for its device extraction flow aimed at controlling
manufacturing variability at the 45nm and beyond. Toshiba said that it
has been addressing manufacturing variability issues with close
cooperation between engineers in their design and device divisions.
Their goal was to develop an advanced systematic device extraction flow
integrated with its lithography flow that could provide more accurate
transistor models incorporating precise effects that become significant
at 45nm and smaller nodes.
“Taking actions at the design stage to minimize manufacturing
variability is essential to maintaining competitive advantage at
advanced process nodes,” said Dr. Fumitomo Matsuoka, Senior Manager of
Advanced Logic Technology Department, System LSI Division at Toshiba.
“Toshiba
is leading the way to the next stage of DFM which involves going beyond
eliminating catastrophic defects and addressing the issues that affect
parametric yield,” said Joseph Sawicki, Vice President and General
Manager of the Design-to-Silicon division at Mentor Graphics. “As
foundries and EDA vendors work together to accurately model the
manufacturing process at advanced nodes, we can have a substantial
impact on overall device yield and performance.”