Early evaluation tools have been shipped to the majority of leading edge chip manufacturers, whether directly or to R&D centres such as IMEC in Belgium to work out how to better control defects.

TSMC has been an early adopter of the technology due in no small part to Burn Lin, TSMC's top lithography guru and an architect of moving immersion into the mainstream.

At SEMICON West this year, I attended as have for many years the lithography breakfast forum, which has presentations from the leading lithography tool vendors and a sprinkling of litho gurus from chip manufacturers. This year Burn Lin was invited back to cover non-other than immersion lithography. However during his presentation he discussed work he and TSMC engineers had done on the ASML immersion tool they have that included a home grown designed and engineered ‘ring' type seal around the water contact area with the bottom lens and wafer that had improved defect levels considerably.

This was the first time we had heard of this work and was not mentioned at the SPIE conference in late February as far as I can recall!

On returning back from SEMICON, I called ASML to enquire about the ‘ring.' Interestingly they knew about Lin's work but had no plans to adopt this on future immersion tools. This would seem to be a Lin invention that goes no further other than the potential for TSMC to then modify all future purchased immersion tools from ASML to the ‘ring' configuration.

Since then it has been announced that Lin has applied for a patent on the ‘ring' so TSMC is taking the invention seriously, which suggests that TSMC may well integrate it into its immersion tools when they start buying them for production purposes. This might well be a competitive advantage for TSMC, especially against rival foundries that also use ASML litho tools!

Below are some drawings of the patent pending design Lin disclosed at SEMICON WEST this year.