Skip Miller, Hans Kattouw & Frank van Bilsen, ASML, Netherlands, & Axel Nackaerts & Staf Verhaegen, IMEC, Belgium

ABSTRACT

Productivity improvements of output in terms of square centimeters per unit time have increased more than 50-fold over the past 20 years. In addition to delivering a lower cost of ownership, the increased productivity also improves fab efficiency. Imaging and overlay improvements deliver IC industry value by enabling aggressive design rules and maximizing die yield. In this paper, a typical industry SRAM structure is used to look at the sensitivity analysis regarding die area compared to overlay and imaging performance. It is found that imaging or resolution improvements via NA and k1 have a big impact on the die area and resulting possible die per wafer. In the example studied, there was a 3.4% gain in die per wafer for every 1% reduction in k1. Overlay reduction has a significant impact on die area as well. In this analysis we concluded that there is approximately a 0.2% gain in die area, or die per wafer, for every 1% reduction in overlay. Finally, die yield sensitivity vs. improvements in imaging and overlay is investigated. At the imaging or overlay specification, the slope of the yield curve is very steep. For the 45nm node, there was an approximately 5% improvement in yield for every 1% reduction in CDU and overlay.