Michael Corbett & Mark Thirsk, Linx Consulting LLC,USA

ABSTRACT

Today, most new logic and ASIC devices are being implemented with multiple copper interconnect layers put down with a dual damascene approach. This article will examine the state-of-the-art in copper CMP polishing for the 90nm node that is currently being ramped into highvolume manufacturing, and look forward to the challenges, needs and trends for the implementation of 65nm and 45nm half-pitch devices.  We also analyze forecasts of unit operations, discuss the dynamics within the supply side of the CMP consumable industry, and look at how novel technologies such as ECMP may impact both users and suppliers. 

30th Edition: The status and future of copper CMP technology and consumables need