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Product Briefing Outline: Synopsys has launched its PrimeYield tool suite that is designed to integrate design with manufacturing by accurately predicting design-induced mechanisms that threaten manufacturing tolerances and by providing automated correction guidance to upstream design implementation tools. PrimeYield provides predictive and corrective actions for manufacturing-sensitive design patterns before tapeout, according to the company. This is due to using production-baseline technology and manufacturing models by the leading foundries and integrated device manufacturers (IDMs). Synopsys reports that PrimeYield can reduce time to yield by 4 to 6 weeks at advanced nodes.

Problem: At 65nm and below, chip production is highly sensitive to process issues, such as lithography errors, chemical-mechanical polishing (CMP) and particle- induced defects. Models do not tend to provide accurate enough inclusion of real world fabrication process induced issues, causing longer DFM learning and potential re-spins.

Solution: PrimeYield simulates the full resolution-enhancement technology (RET) tapeout flow using the same production-baseline technology and manufacturing models used by today's leading foundries and integrated device manufacturers, and reports lithographic sensitivities in the layout. PrimeYield LCC ranks problems by severity and presents them to the designer for review. For customers who own IC Compiler, the problems can be repaired automatically, based on a set of coded correction rules, according to the company. To address critical issues, the PrimeYield tool suite includes several individual but tightly linked modules. In lithography compliance checking (LCC), simulation runs, flag potential lithographical errors and process-variation effects for the designer earlier in the design process and provide ‘escapes' in a designer friendly format. With CMP modeling the software flags planarity issues such as poor focus across the wafer surface as well as locating and analyzing uneven metal fill, which is a source of systematic failures in advanced chip designs. Critical area analysis (CAA), enables analysis and improvement of critical areas with higher probability of yield loss in the design layout due to typical areas prone to random defects, especially in thin lines and tight layout areas. Overall, PrimeYield is designed to provide greater accuracy with respect to real world processing issues, while allowing real escapes to avoid extra effort on false positives at the design stage.

Applications: 65nm and below IC designs.

Platform: PrimeYield is tightly linked to design implementation. PrimeYield drives automatic correction within Synopsys' IC Compiler advanced physical implementation solution and accurate parasitic extraction within the Star-RCXT tool. Enhancements to the Star- RCXT extraction tool and the Synopsys PrimeTime(R) static timing analysis tool have recently been made. PrimeYield list pricing starts at $225,000 per module.


Availability: July 2006 onwards.