Online information source for semiconductor professionals
Interconnect Strategies and Deep Submicron CMOS Manufacture
Popular articles
Micron moving fast on Hynix in Q208 NAND flash rankings, says iSuppli - 19 August 2008
Numonyx to close California Technology Center - 12 August 2008
Qimonda starts major reorganization: exits PC DRAM market - 13 October 2008
Micron close to Inotera share purchase, says Gartner - 06 October 2008
Applied Materials sees higher CapEx spending for 2009 - 15 August 2008
KENNETH ROSE & CHRISTOPHER MARK, Rensselaer Polytechnic Institute, Troy, NY, USA
ABSTRACT
As CMOS chips are scaled to deep submicron dimensions, interconnects increasingly limit performance. Achieving performance requirements can lead to an explosion in the number of wiring levels required. Alternative approaches to limiting long wire delay and reducing the number of wiring levels are discussed. Tradeoffs in interconnect strategies are compared.
 |
Please login to download the paper. No account yet? Please register. It's free! |