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Home arrow News arrow Wafer Processing arrow SEZ to enter resist-strip market with single wafer wet process technology
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SEZ to enter resist-strip market with single wafer wet process technology Print E-mail
Jul 19, 2006 at 03:29 PM
ImageThe SEZ Group has been quietly working with a wide range of existing customers to develop volume manufacturing solutions for photoresist-removal steps using its single wafer all-wet processing technology and tool platforms. The company announced during Semicon West that its aim was to finish off current process evaluation programs with key customers from the memory, logic and foundry sectors using is current single-chamber R&D tool in readiness for a multi-chamber FEOL production tool to be introduced later in 2006.

The evaluation work is centered on a novel chemical process that is intended to streamline front-end-of-line (FEOL) photoresist-strip processes.  SEZ has developed a proprietary ‘Enhanced Sulfuric Acid' (‘ESA') strip process which has been designed to employ a range of sulfuric acid-based chemistries to reduce the number of steps in photoresist-removal processes. Currently the majority of resist-strip steps are undertaken using a variety of plasma ashing techniques with as many as 20 steps in the FEOL.
 
"As with all our technology, our solution for FEOL photoresist-removal applications is designed to meet customers' immediate, pressing needs, as well as creates a prime opportunity to implement a single-wafer approach in the FEOL space," stated Kurt Lackenbucher, executive vice president and chief operating officer for the SEZ Group. "The combination of the ESA strip process and our forthcoming FEOL platform will create a fast-throughput, high-performance solution that enables photoresist removal and residue clean-up in one flexible, single-wafer tool. This represents the next strategic step along our technology roadmap focused on anticipating customer needs to facilitate the deployment of single-wafer technology throughout the entire fab," noted Lackenbucher.

SEZ has developed processes that can be handled by one tool that covers strip, photoresist rework, post-ash residue strip, post-etch resist removal as well as post-implant resist removal for all implant doses and species, according to the company.

So far the development work with key customers has shown that the sulfuric acid cleans at temperatures up to 140°C have successfully removed both i-line and deep-ultraviolet (DUV) resists without the problems of selectivity and defectivity that can be encountered with plasma ashing techniques.

SEZ also believes that as advanced devices can typically require the stripping of implanted resist as much as 15 times, performing the sequence repeatedly can lead to significant cumulative silicon loss that degrades transistor performance due to the oxidation of silicon under plasma ash conditions and subsequent removal of the oxide via wet clean. The ITRS also calls for substrate losses of no more than 0.5 angstroms per pass for both silicon and silicon dioxide materials by 2007, falling to 0.3 angstroms by 2010. SEZ believes that these targets will be very difficult for dry plasma ashers to meet.

However, conventional dry strip technology continues to be enhanced as seen with the launch by Novellus Systems at this years Semicon West show of its new GAMMA Express dry strip system that is also targeting the 65nm and 45nm node process requirements. The system is currently in beta evaluation with a large memory manufacturer in Asia, and has its production release in the fourth quarter of 2006, according to Novellus.

Novellus claims the tool has low silicon loss in implant strip and non-oxidizing strip chemistries enclosed in a platform capable of 300 wph for bulk strip and 150 wph for high dose implant strip (HDIS). Sass Somekh, President of Novellus Systems told Semiconductor Fabtech during Semicon West that the GAMMA Express was a significant improvement over previous renditions, providing the company with significant new business opportunities, while reiterating a ‘zero removal damage' capability for the new tool.

Business opportunities would seem to be the key as the leading resist-strip company Mattson Technology highlighted to Semiconductor Fabtech at Semicon West this year that the Total Available Market (TAM) for strip tools would reach $740 million US dollars by 2008.

Its new Suprema tool uses an enhanced RF plasma source, based on Mattson's proprietary inductively coupled plasma (ICP) technology that will be used by Toshiba for both bulk and high-dose implant stripping applications to produce advanced sub-90 nanometer NAND flash devices that was announced last week at Semicon West.

With both the technology challenges and business opportunities up for grabs, especially at the 45nm node, competition in the resist strip market is set to intensify. SEZ may be seen as the new kid on blog from a resist strip perspective but as history has shown in other single wafer wet processing environments its customizable process platforms and process chemistries have become standard steps in some critical BEOL steps, especially in respect to 300mm wafer processing. Last year at the show company executives announced that a key strategic move in the coming years for the company would be penetrating FEOL critical processes. Resist strip is one it would seem they are definitely after!


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